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TMS320DM368ZCE TMS320DM368ZCEDF Mosfet Power Transistor DSP, DSC Digital Media SOC

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TMS320DM368ZCE TMS320DM368ZCEDF Mosfet Power Transistor DSP, DSC Digital Media SOC

Brand Name : Ti

Model Number : TMS320DM368ZCE

Maximum Clock Frequency : 432 MHz

L1 Cache Instruction Memory : 16 kB

L1 Cache Data Memory : 8 kB

Data RAM Size : 32 kB

Operating Supply Voltage : 1.35 V

Minimum Operating Temperature : - 40 C

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TMS320DM368ZCE TMS320DM368ZCEDF Mosfet Power Transistor DSP, DSC Digital Media SOC

1 Features

  • Highlights
  • – High-Performance Digital Media
    System-on-Chip (DMSoC)

  • – 432-MHz ARM926EJ-S Clock Rate

  • – Two Video Image Co-processors
    (HDVICP, MJCP) Engines

  • – Supports a Range of Encode, Decode, and
    Video Quality Operations

  • – Video Processing Subsystem

    • HW Face Detect Engine

    • Resize Engine from 1/16x to 8x

    • 16-Bit Parallel AFE (Analog Front-End)
      Interface Up to 120 MHz

    • 4:2:2 (8-/16-bit) Interface

    • 8-/16-bit YCC and Up to 24-Bit RGB888
      Digital Output

    • 3 DACs for HD Analog Video Output

    • Hardware On-Screen Display (OSD)

  • – Capable of 1080p 30fps H.264 video processing

  • – Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan

  • – 8 Different Boot Modes and Configurable Power-Saving Modes

  • – Pin-to-pin and software compatible with DM365

  • – Extended temperature (-40oC – 85oC) available

  • – 3.3-V and 1.8-V I/O, 1.35-V Core

  • – 338-Pin Ball Grid Array at 65nm Process
    Technology

• High-Performance Digital Media

device
• ARM926EJ-STM Core

– Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
– DSP Instruction Extensions and Single Cycle MAC
– ARM® Jazelle® Technology
– Embedded ICE-RT Logic for Real-Time

Debug
• ARM9 Memory Architecture

– 16K-Byte Instruction Cache – 8K-Byte Data Cache
– 32K-Byte RAM
– 16K-Byte ROM

– Little Endian
• Two Video Image Co-processors

(HDVICP, MJCP) Engines
– Support a Range of Encode and Decode

Operations
– H.264, MPEG4, MPEG2, MJPEG, JPEG,

WMV9/VC1
• Video Processing Subsystem

– Front End Provides:

  • HW Face Detect Engine

  • Hardware IPIPE for Real-Time Image
    Processing

– Resize Engine

  • – Resize Images From 1/16x to 8x

  • – Separate Horizontal/Vertical
    Control

  • – Two Simultaneous Output Paths

  • IPIPE Interface (IPIPEIF)

  • Image Sensor Interface (ISIF) and CMOS
    Imager Interface

  • 16-Bit Parallel AFE (Analog Front End)
    Interface Up to 120 MHz

  • Glueless Interface to Common Video
    Decoders

  • BT.601/BT.656/BT.1120 Digital YCbCr
    4:2:2 (8-/16-Bit) Interface

  • Histogram Module

System-on-Chip (DMSoC)

  • – 432-MHz ARM926EJ-S Clock Rate

  • – 4:2:2 (8-/16-Bit) Interface

  • – Capable of 1080p 30fps H.264 video
    processing

  • – Pin compatible with DM365 processors

  • – Fully Software-Compatible With ARM9TM

  • – Extended temperature available for 432-MHz




































Product Tags:

mosfet motor control circuit

      

n channel mos field effect transistor

      
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